1. Field of the Invention
The present invention relates generally to the field of semiconductor devices, and more particularly to metal gate structures having gate trenches with different widths.
2. Description of the Prior Art
With the trend of miniaturization in the semiconductor industry with corresponding improvements in semiconductor manufacturing processes, manufactures are able to form both dense regions and sparse regions on one chip.
During an etching process of fabricating patterned structures, however, etching rates in the dense regions are often different from those in the sparse regions due to density difference. In general, the etching rate in the dense region is lower than that in the sparse regions. Hence, for trenches respectively formed in the dense regions and the sparse regions, their depths often deviate from their predetermined values after the above-mentioned etching process. For example, the trenches in the sparse regions are usually deeper than those in the dense regions, which may cause a pre-layer to be exposed from the bottom of the trenches and negatively affect the electrical propertied of the corresponding semiconductor devices.